Semiconductor devices include one or more integrated circuits that can be used to store data, process electronic signals, etc. Such semiconductor devices are used in virtually all modern electronic devices. There are several different types of semiconductor devices used in modern electronics including, for example, memory devices, electronic signal processors, devices for capturing or acquiring images, etc. Each of these semiconductor devices typically comprises a plurality of transistors, which can be used as gates or switches for electrical signals. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a common type of transistor useful in high speed switching applications and integrated circuits. A typical MOSFET includes a metal-insulator structure, often referred to as a “gate,” between lightly-doped drain (LDD) extension regions in a semiconductor substrate.
FIG. 1 is a schematic cross-sectional view of a transistor 10 that may be used in a memory cell of a conventional non-volatile memory device. The transistor 10 may be fabricated on or in a substrate 12, which may comprise a doped semiconductor material. The transistor 10 includes a gate stack 22 formed between LDD extension regions 24 in the substrate 12. The LDD extension regions 24 may comprise, for example, doped regions in or on the substrate 12, which itself may be doped of opposite polarity relative to the LDD extension regions 24. For example, the LDD extension regions 24 may comprise n-doped regions in or on the substrate 12, and the substrate 12 may be p-doped, at least in the region thereof between the LDD extension regions 24, so as to provide an np-type structure in the substrate 12 below the gate stack 22. The gate stack 22 is electrically isolated from the substrate 12 by the gate oxide 14. The gate stack 22 is typically formed by conventional methods and includes a conductive polysilicon material 16. As polysilicon resistivity is considerably higher than that of tungsten (W) or other metals, a tungsten layer 18 is typically employed over the polysilicon material 16 in order to decrease resistance while retaining the gate integrity.
The gate stack 22 is conventionally formed using masking and etching processes to respectively remove portions of a nitride material 20, the tungsten layer 18, and the polysilicon material 16 through an aperture in a mask (not shown). This process exposes a cross section of the device layers on the sidewalls 27 of the gate stack 22. Typically, during the etching process the gate oxide 14 is employed as an etch stop. Etching tends to cause considerable damage to a surface 26 of the gate oxide 14 adjacent the gate stack 22, as shown in FIG. 1. Such damage occurs regardless of efforts to optimize etch selectivity and optical end point measurement techniques. The etch damage may also extend to the underlying substrate 12.
Damage to the gate oxide 14 caused by plasma etching may cause susceptibility to hot carrier effects and may cause defects such as charge trapping, and current leakage. Aside from the illustrated physical thinning, plasma etching tends to damage oxide bonds, creating charge trap sites. Structural damage often extends laterally under the gate as well as over adjacent LDD extension regions 24. Such defects result in an increased threshold voltage and unreliable circuit operation. As a high quality gate insulator is required for reliable operation of the transistor 10 and of the circuit employing the transistor 10, this damage must be repaired to improve the quality and life expectancy of the gate oxide 14.
Selective oxidation of the gate oxide, often referred to as “source/drain reoxidation,” is employed to repair portions of the surface damaged during the gate formation. Source/drain reoxidation typically involves thermal oxidation of the semiconductor substrate to grow new oxide material. During thermal oxidation, the semiconductor substrate is exposed to oxygen gas or water at high temperatures (e.g., 700° C.-1200° C.) for a relatively long period of time. The high temperature oxidizing gas reacts with the semiconductor substrate to produce an oxide material.
While the reaction of the oxidizing gas with the substrate during thermal oxidation repairs the damaged gate oxide, the oxidizing gas may also contact and potentially react with any exposed gate materials. Thermal oxidation is problematic because some metals, such as tungsten (W), are so readily oxidized that overall gate resistance is increased beyond tolerable levels. For example, tungsten begins to oxidize to tungsten trioxide (WO3) at temperatures of approximately 250° C. Thus, in the presence of high temperatures necessary for thermal oxidation, oxygen gas may also undesirably react with a conductive line, compromising integrity of the conductive line and increasing resistance of the device. As shown in FIG. 2, one method of preventing degradation of the gate stack 22 during source/drain reoxidation is to form a protective barrier covering the sidewalls 27 of the gate stack 22. For example, U.S. Pat. No. 5,998,290 to Wu et al. describes the use of a partial nitride spacer etch used to for nitride spacers 29 that preserves the integrity of the sidewalls 27. After the nitride material 20, the tungsten layer 18 and a portion of the polysilicon material 16 are patterned by plasma etching, a nitride layer (not shown) is deposited over the sidewalls 27 of the gate stack 22 and exposed regions of the polysilicon material 16. The nitride spacers 29 act as a protective barrier preventing degradation of conductive material 18 during source/drain reoxidation.
However, as minimum feature size and critical dimensions continue to decrease, nitride spacers cannot be scaled accordingly. The nitride spacers trap electrons, causing an increase in parasitic resistance. Deposition process limitations prevent the formation of defect-free nitride spacers with thicknesses less than about eighty nanometers (80 nm). Accordingly, the charge-trapping nitride spacers prevent the critical dimension of the polysilicon material of the conductive line from being decreased. For example, in a transistor with a thirty-five nanometer (35 nm) conductive line, the nitride spacers and, thus, the polysilicon material, are at least 120 Å (e.g., about half the critical dimension). The inability to reduce the area of the charge-trapping nitride spacers, in combination with a decrease in the cross-sectional area of the gate, leads to an undesirable increase in gate resistance. Furthermore, current methods limit the size of the device by preventing a decrease in the critical dimensions of polysilicon material. Thus, while the nitride spacers may prevent oxidation of the gate stack, they also limit the feature size of the resulting device.
For the reasons stated above, and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved methods of gate fabrication and associated structures that can be scaled to smaller feature sizes without causing an undesirable increase in gate resistance.